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authorBjorn Helgaas <bhelgaas@google.com>2021-09-02 14:56:51 -0500
committerBjorn Helgaas <bhelgaas@google.com>2021-09-02 14:56:51 -0500
commiteccefc748e0edbb3ae8be846c4cd17bc20397898 (patch)
tree0c85577b845e43ea28a03c791a8c6415e04b3926 /drivers/pci
parent09cfc9db2db1a0c7a38033b16e2471c7c6becaf8 (diff)
parentde0a01f5296651d3a539f2d23d0db8f359483696 (diff)
Merge branch 'remotes/lorenzo/pci/xilinx-nwl'
- Document optional clock DT property (Michal Simek) - Enable PCIe ref clock (Hyun Kwon) * remotes/lorenzo/pci/xilinx-nwl: PCI: xilinx-nwl: Enable the clock through CCF dt-bindings: pci: xilinx-nwl: Document optional clock property
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/controller/pcie-xilinx-nwl.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 3d178d5b652b..a72b4f9a2b00 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -6,6 +6,7 @@
* (C) Copyright 2014 - 2015, Xilinx, Inc.
*/
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@@ -169,6 +170,7 @@ struct nwl_pcie {
u8 last_busno;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
+ struct clk *clk;
raw_spinlock_t leg_mask_lock;
};
@@ -816,6 +818,16 @@ static int nwl_pcie_probe(struct platform_device *pdev)
return err;
}
+ pcie->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(pcie->clk))
+ return PTR_ERR(pcie->clk);
+
+ err = clk_prepare_enable(pcie->clk);
+ if (err) {
+ dev_err(dev, "can't enable PCIe ref clock\n");
+ return err;
+ }
+
err = nwl_pcie_bridge_init(pcie);
if (err) {
dev_err(dev, "HW Initialization failed\n");