Merge branch 'pci/endpoint' into next

* pci/endpoint:
  tools: PCI: Add a missing option help line
  misc: pci_endpoint_test: Enable/Disable MSI using module param
  misc: pci_endpoint_test: Avoid using hard-coded BAR sizes
  misc: pci_endpoint_test: Add support to not enable MSI interrupts
  misc: pci_endpoint_test: Add support to provide aligned buffer addresses
  misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR
  PCI: designware-ep: Do not disable BARs during initialization
  PCI: dra7xx: Reset all BARs during initialization
  PCI: dwc: designware: Provide page_size to pci_epc_mem
  PCI: endpoint: Remove the ->remove() callback
  PCI: endpoint: Add support to poll early for host commands
  PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs
  PCI: endpoint: Do not reset *command* inadvertently
  PCI: endpoint: Add "volatile" to pci_epf_test_reg
  PCI: endpoint: Add support for configurable page size
  PCI: endpoint: Make ->remove() callback optional
  PCI: endpoint: Add an API to get matching "pci_epf_device_id"
  PCI: endpoint: Use of_dma_configure() to set initial DMA mask

1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index ced9319cf76a..1e2aaedbebf2 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -337,10 +337,23 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+	u32 reg;
+
+	reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+	dw_pcie_writel_dbi2(pci, reg, 0x0);
+	dw_pcie_writel_dbi(pci, reg, 0x0);
+}
+
 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+	enum pci_barno bar;
+
+	for (bar = BAR_0; bar <= BAR_5; bar++)
+		dw_pcie_ep_reset_bar(pci, bar);
 
 	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
 }