diff options
| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-11-02 19:30:41 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-11-03 14:21:06 +0000 |
| commit | 5f15d392dcb4aa250a63d6f2c5adfc26c0aedc78 (patch) | |
| tree | 32bc16133e832da12436e7c3d179fc1adf9be856 /drivers/net | |
| parent | 563bcbae3ba233c275c244bfce2efe12938f5363 (diff) | |
net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled
Some device set MAC06 exchange in the bootloader. This cause some
problem as we don't support this strange mode and we just set the port6
as the primary CPU port. With MAC06 exchange, PAD0 reg configure port6
instead of port0. Add an extra check and explicitly disable MAC06 exchange
to correctly configure the port PAD config.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Fixes: 3fcf734aa482 ("net: dsa: qca8k: add support for cpu port 6")
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/dsa/qca8k.c | 8 | ||||
| -rw-r--r-- | drivers/net/dsa/qca8k.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index ea7f12778922..a429c9750add 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1109,6 +1109,14 @@ qca8k_setup(struct dsa_switch *ds) if (ret) return ret; + /* Make sure MAC06 is disabled */ + ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL, + QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); + if (ret) { + dev_err(priv->dev, "failed disabling MAC06 exchange"); + return ret; + } + /* Enable CPU Port */ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index e10571a398c9..128b8cf85e08 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -34,6 +34,7 @@ #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 +#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31) #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) #define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) #define QCA8K_REG_PORT5_PAD_CTRL 0x008 |