diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2011-04-20 07:57:36 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-04-21 17:05:55 -0700 |
| commit | eb07a9408e05f67caa671bdf2a509a4d2bd05abf (patch) | |
| tree | e17b801356317ffa1225c2cb19e9580649d528fb /drivers/net/tg3.h | |
| parent | 4d95847381228639844c7197deb8b2211274ef22 (diff) | |
tg3: Adjust rx prod ring bd replenish thresholds
The oldest tg3 devices had large rx producer ring BD caches. Back then,
it made sense to make the BD cache replenish threshold only a function
of the number of rx buffers posted by the driver. Since then, the BD
cache sizes have shrunk to 25% of their original size and, in some
cases, the ring sizes have quadrupled in size. Under such conditions,
static BD cache replenish thresholds no longer match the hardware
constraints.
This patch attempts to factor in the BD cache size into the bd cache
replenish strategy, taking the existing hardware bugs into account.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index db50bfe046e4..dd331f8d3f7a 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -23,8 +23,6 @@ #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ #define TG3_BDINFO_SIZE 0x10UL -#define TG3_RX_INTERNAL_RING_SZ_5906 32 - #define TG3_RX_STD_MAX_SIZE_5700 512 #define TG3_RX_STD_MAX_SIZE_5717 2048 #define TG3_RX_JMB_MAX_SIZE_5700 256 @@ -2136,6 +2134,13 @@ #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 +#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 + +#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 +#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 + /* Currently this is fixed. */ #define TG3_PHY_MII_ADDR 0x01 |