diff options
| author | Alex Elder <elder@linaro.org> | 2020-09-28 18:04:41 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-09-28 18:34:56 -0700 |
| commit | e6580d0eb7f479473c9fdc1da0a2ac37ccf00d6e (patch) | |
| tree | 2bb0572ed8bc0b7b90c32b02fac340523edff8d2 /drivers/net/ipa | |
| parent | e0ebe204916a0f9915185268ad4735eaa7adc59d (diff) | |
net: ipa: share field mask values for GSI interrupt type
The GSI interrupt type register and interrupt type mask register
have the same field bits at the same locations. Use a common set of
field masks for both registers rather than essentially duplicating
them. The only place the interrupt mask register uses any of these
is in gsi_irq_enable().
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ipa')
| -rw-r--r-- | drivers/net/ipa/gsi.c | 4 | ||||
| -rw-r--r-- | drivers/net/ipa/gsi_reg.h | 17 |
2 files changed, 7 insertions, 14 deletions
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index cb75f7d54057..745717477cad 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -254,8 +254,8 @@ static void gsi_irq_enable(struct gsi *gsi) /* We don't use inter-EE channel or event interrupts */ val = GSI_CNTXT_TYPE_IRQ_MSK_ALL; - val &= ~MSK_INTER_EE_CH_CTRL_FMASK; - val &= ~MSK_INTER_EE_EV_CTRL_FMASK; + val &= ~INTER_EE_CH_CTRL_FMASK; + val &= ~INTER_EE_EV_CTRL_FMASK; iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); val = GENMASK(gsi->channel_count - 1, 0); diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index acc9e744c67d..598db57a68df 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -258,6 +258,11 @@ GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ (0x0001f080 + 0x4000 * (ee)) +#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ + GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) +#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ + (0x0001f088 + 0x4000 * (ee)) +/* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */ #define CH_CTRL_FMASK GENMASK(0, 0) #define EV_CTRL_FMASK GENMASK(1, 1) #define GLOB_EE_FMASK GENMASK(2, 2) @@ -265,18 +270,6 @@ #define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) #define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) #define GENERAL_FMASK GENMASK(6, 6) - -#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ - (0x0001f088 + 0x4000 * (ee)) -#define MSK_CH_CTRL_FMASK GENMASK(0, 0) -#define MSK_EV_CTRL_FMASK GENMASK(1, 1) -#define MSK_GLOB_EE_FMASK GENMASK(2, 2) -#define MSK_IEOB_FMASK GENMASK(3, 3) -#define MSK_INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) -#define MSK_INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) -#define MSK_GENERAL_FMASK GENMASK(6, 6) #define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0) #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ |