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authorHuang, Xiong <xiong@qca.qualcomm.com>2012-04-30 15:38:54 +0000
committerDavid S. Miller <davem@davemloft.net>2012-04-30 21:44:14 -0400
commitf56fa56737291df19cd1a9089ade76c59f231212 (patch)
treeaec16ab098d53e32510b961b08b29c3bb941010c /drivers/net/ethernet/atheros
parent229e6b6e9cdc615abb10336792bcb94a34ba6532 (diff)
atl1c: enlarge L1 response waiting timer
The hardware incorrectly process L0S/L1 entrance if the chipset/root response after specific/shorter timer and cause system hang. Enlarge the timeout value to avoid this issue. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/atheros')
-rw-r--r--drivers/net/ethernet/atheros/atl1c/atl1c_hw.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 21a5bc1dc1f2..17d935bdde0a 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -157,7 +157,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL
#define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @
* ->L0s not L1 */
-#define PM_CTRL_PM_REQ_TO_DEF 0xC
+#define PM_CTRL_PM_REQ_TO_DEF 0xF
#define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
#define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */
#define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16