diff options
| author | Adrian Hunter <adrian.hunter@intel.com> | 2014-09-24 10:27:33 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2014-10-03 14:25:35 +0200 |
| commit | a06586b62db5c63752e2e68daffec4baa275d594 (patch) | |
| tree | 3da1e5d5ee615be0a41c1e811f08fa8b6510dfc1 /drivers/mmc | |
| parent | f5fa92e58bce2cbcce99c2c5260c0b338a1ef201 (diff) | |
mmc: sdhci-pci: Fix Braswell eMMC timeout clock frequency
Braswell eMMC host controller specifies an incorrect
timeout clock frequncy in the capabilities registers.
The correct value is 1 MHz.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-pci.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index 4ca6ae6a175d..61192973e7cb 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -272,6 +272,8 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR; slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; slot->hw_reset = sdhci_pci_int_hw_reset; + if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) + slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ return 0; } |