diff options
| author | Yann Gautier <yann.gautier@foss.st.com> | 2023-06-19 13:51:18 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2023-06-20 11:44:40 +0200 |
| commit | 27bdc37c390af01af72ad3750cafe19b459bdf93 (patch) | |
| tree | 74dd09bc34530862de37efd86c8d17ada695e219 /drivers/mmc | |
| parent | ea9ca04119734c2b84691276fef2c018e9fd68ae (diff) | |
mmc: mmci: stm32: manage block gap hardware flow control
In stm32 sdmmc variant revision v3.0, a block gap hardware flow control
should be used with bus speed modes SDR104 and HS200.
It is enabled by writing a non-null value to the new added register
MMCI_STM32_FIFOTHRR.
The threshold will be 2^(N-1) bytes, so we can use the ffs() function to
compute the value N to be written to the register. The threshold used
should be the data block size, but must not be bigger than the FIFO size.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Link: https://lore.kernel.org/r/20230619115120.64474-5-yann.gautier@foss.st.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/mmci.h | 5 | ||||
| -rw-r--r-- | drivers/mmc/host/mmci_stm32_sdmmc.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index b1968cafc58b..361954249d04 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -218,6 +218,11 @@ #define MCI_STM32_BUSYD0ENDMASK BIT(21) #define MMCIMASK1 0x040 + +/* STM32 sdmmc data FIFO threshold register */ +#define MMCI_STM32_FIFOTHRR 0x044 +#define MMCI_STM32_THR_MASK GENMASK(3, 0) + #define MMCIFIFOCNT 0x048 #define MMCIFIFO 0x080 /* to 0x0bc */ diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c index 1bc775b9e714..29634d1dc289 100644 --- a/drivers/mmc/host/mmci_stm32_sdmmc.c +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c @@ -361,6 +361,19 @@ static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) datactrl = mmci_dctrl_blksz(host); + if (host->hw_revision >= 3) { + u32 thr = 0; + + if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 || + host->mmc->ios.timing == MMC_TIMING_MMC_HS200) { + thr = ffs(min_t(unsigned int, host->data->blksz, + host->variant->fifosize)); + thr = min_t(u32, thr, MMCI_STM32_THR_MASK); + } + + writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR); + } + if (host->mmc->card && mmc_card_sdio(host->mmc->card) && host->data->blocks == 1) datactrl |= MCI_DPSM_STM32_MODE_SDIO; |