diff options
author | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2018-01-04 13:08:56 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2018-01-04 13:15:05 -0500 |
commit | 6e6a8b5a38cb04d5ef35d4eb57836126b954e7c8 (patch) | |
tree | 1ea9d8dbba617094c1f8ae2ff4806eeb868ee2c3 /drivers/media/dvb-frontends | |
parent | 4a3fad709bbc74c85fffff8903d17b5e35723365 (diff) |
media: replace all <spaces><tab> occurrences
There are a lot of places where sequences of space/tabs are
found. Get rid of all spaces before tabs.
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'drivers/media/dvb-frontends')
-rw-r--r-- | drivers/media/dvb-frontends/au8522_priv.h | 218 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/drx39xyj/drx_driver.h | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stb0899_drv.c | 10 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stb0899_drv.h | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stb0899_priv.h | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv0900_core.c | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv0900_init.h | 34 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv0900_priv.h | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv090x.c | 12 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv090x_priv.h | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv6110x.c | 2 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/stv6110x_priv.h | 6 | ||||
-rw-r--r-- | drivers/media/dvb-frontends/tda10023.c | 2 |
13 files changed, 148 insertions, 148 deletions
diff --git a/drivers/media/dvb-frontends/au8522_priv.h b/drivers/media/dvb-frontends/au8522_priv.h index f02dac958db6..2043c1744753 100644 --- a/drivers/media/dvb-frontends/au8522_priv.h +++ b/drivers/media/dvb-frontends/au8522_priv.h @@ -99,7 +99,7 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7 -#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8 +#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8 #define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A9 #define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA #define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB @@ -110,18 +110,18 @@ int au8522_led_ctrl(struct au8522_state *state, int led); /* Receiver registers */ #define AU8522_FRMREGTHRD1_REG0B0H 0x0B0 -#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1 -#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2 -#define AU8522_TOREGAGC1_REG0B3H 0x0B3 -#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4 +#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1 +#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2 +#define AU8522_TOREGAGC1_REG0B3H 0x0B3 +#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4 #define AU8522_FRMREGBBH_REG0B5H 0x0B5 -#define AU8522_FRMREGBBM_REG0B6H 0x0B6 -#define AU8522_FRMREGBBL_REG0B7H 0x0B7 +#define AU8522_FRMREGBBM_REG0B6H 0x0B6 +#define AU8522_FRMREGBBL_REG0B7H 0x0B7 /* 0xB8 TO 0xD7 are the filter coefficients */ -#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8 -#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9 -#define AU8522_TOREGAGC2_REG0DAH 0x0DA -#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB +#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8 +#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9 +#define AU8522_TOREGAGC2_REG0DAH 0x0DA +#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB #define AU8522_FRMREGPILOTH_REG0DCH 0x0DC #define AU8522_FRMREGPILOTM_REG0DDH 0x0DD #define AU8522_FRMREGPILOTL_REG0DEH 0x0DE @@ -134,9 +134,9 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_CHIP_MODE_REG0FEH 0x0FE /* I2C bus control registers */ -#define AU8522_I2C_CONTROL_REG0_REG090H 0x090 -#define AU8522_I2C_CONTROL_REG1_REG091H 0x091 -#define AU8522_I2C_STATUS_REG092H 0x092 +#define AU8522_I2C_CONTROL_REG0_REG090H 0x090 +#define AU8522_I2C_CONTROL_REG1_REG091H 0x091 +#define AU8522_I2C_STATUS_REG092H 0x092 #define AU8522_I2C_WR_DATA0_REG093H 0x093 #define AU8522_I2C_WR_DATA1_REG094H 0x094 #define AU8522_I2C_WR_DATA2_REG095H 0x095 @@ -156,48 +156,48 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_ENA_USB_REG101H 0x101 -#define AU8522_I2S_CTRL_0_REG110H 0x110 -#define AU8522_I2S_CTRL_1_REG111H 0x111 -#define AU8522_I2S_CTRL_2_REG112H 0x112 +#define AU8522_I2S_CTRL_0_REG110H 0x110 +#define AU8522_I2S_CTRL_1_REG111H 0x111 +#define AU8522_I2S_CTRL_2_REG112H 0x112 -#define AU8522_FRMREGFFECONTROL_REG121H 0x121 -#define AU8522_FRMREGDFECONTROL_REG122H 0x122 +#define AU8522_FRMREGFFECONTROL_REG121H 0x121 +#define AU8522_FRMREGDFECONTROL_REG122H 0x122 -#define AU8522_CARRFREQOFFSET0_REG201H 0x201 +#define AU8522_CARRFREQOFFSET0_REG201H 0x201 #define AU8522_CARRFREQOFFSET1_REG202H 0x202 #define AU8522_DECIMATION_GAIN_REG21AH 0x21A -#define AU8522_FRMREGIFSLP_REG21BH 0x21B -#define AU8522_FRMREGTHRDL2_REG21CH 0x21C -#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D +#define AU8522_FRMREGIFSLP_REG21BH 0x21B +#define AU8522_FRMREGTHRDL2_REG21CH 0x21C +#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D #define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E -#define AU8522_FRMREGPLLMODE_REG21FH 0x21F -#define AU8522_FRMREGCSTHRD_REG220H 0x220 -#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221 -#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222 -#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223 -#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224 -#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225 -#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226 +#define AU8522_FRMREGPLLMODE_REG21FH 0x21F +#define AU8522_FRMREGCSTHRD_REG220H 0x220 +#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221 +#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222 +#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223 +#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224 +#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225 +#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226 #define AU_FRMREGPLLACQPHASESCL_REG227H 0x227 -#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228 +#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228 /* Analog TV Decoder */ #define AU8522_TVDEC_STATUS_REG000H 0x000 #define AU8522_TVDEC_INT_STATUS_REG001H 0x001 -#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002 +#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002 #define AU8522_TVDEC_SHARPNESSREG009H 0x009 #define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A #define AU8522_TVDEC_CONTRAST_REG00BH 0x00B #define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C #define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D #define AU8522_TVDEC_HUE_H_REG00EH 0x00E -#define AU8522_TVDEC_HUE_L_REG00FH 0x00F +#define AU8522_TVDEC_HUE_L_REG00FH 0x00F #define AU8522_TVDEC_INT_MASK_REG010H 0x010 #define AU8522_VIDEO_MODE_REG011H 0x011 #define AU8522_TVDEC_PGA_REG012H 0x012 #define AU8522_TVDEC_COMB_MODE_REG015H 0x015 -#define AU8522_REG016H 0x016 +#define AU8522_REG016H 0x016 #define AU8522_TVDED_DBG_MODE_REG060H 0x060 #define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061 #define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062 @@ -207,13 +207,13 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066 #define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067 #define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068 -#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069 +#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A -#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B -#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C -#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D -#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E -#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F +#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B +#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C +#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D +#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E +#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070 #define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073 #define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077 @@ -229,42 +229,42 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401 #define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402 -#define AU8522_FILTER_COEF_R410 0x410 -#define AU8522_FILTER_COEF_R411 0x411 -#define AU8522_FILTER_COEF_R412 0x412 -#define AU8522_FILTER_COEF_R413 0x413 -#define AU8522_FILTER_COEF_R414 0x414 -#define AU8522_FILTER_COEF_R415 0x415 -#define AU8522_FILTER_COEF_R416 0x416 -#define AU8522_FILTER_COEF_R417 0x417 -#define AU8522_FILTER_COEF_R418 0x418 -#define AU8522_FILTER_COEF_R419 0x419 -#define AU8522_FILTER_COEF_R41A 0x41A -#define AU8522_FILTER_COEF_R41B 0x41B -#define AU8522_FILTER_COEF_R41C 0x41C -#define AU8522_FILTER_COEF_R41D 0x41D -#define AU8522_FILTER_COEF_R41E 0x41E -#define AU8522_FILTER_COEF_R41F 0x41F -#define AU8522_FILTER_COEF_R420 0x420 -#define AU8522_FILTER_COEF_R421 0x421 -#define AU8522_FILTER_COEF_R422 0x422 -#define AU8522_FILTER_COEF_R423 0x423 -#define AU8522_FILTER_COEF_R424 0x424 -#define AU8522_FILTER_COEF_R425 0x425 -#define AU8522_FILTER_COEF_R426 0x426 -#define AU8522_FILTER_COEF_R427 0x427 -#define AU8522_FILTER_COEF_R428 0x428 -#define AU8522_FILTER_COEF_R429 0x429 -#define AU8522_FILTER_COEF_R42A 0x42A -#define AU8522_FILTER_COEF_R42B 0x42B -#define AU8522_FILTER_COEF_R42C 0x42C -#define AU8522_FILTER_COEF_R42D 0x42D +#define AU8522_FILTER_COEF_R410 0x410 +#define AU8522_FILTER_COEF_R411 0x411 +#define AU8522_FILTER_COEF_R412 0x412 +#define AU8522_FILTER_COEF_R413 0x413 +#define AU8522_FILTER_COEF_R414 0x414 +#define AU8522_FILTER_COEF_R415 0x415 +#define AU8522_FILTER_COEF_R416 0x416 +#define AU8522_FILTER_COEF_R417 0x417 +#define AU8522_FILTER_COEF_R418 0x418 +#define AU8522_FILTER_COEF_R419 0x419 +#define AU8522_FILTER_COEF_R41A 0x41A +#define AU8522_FILTER_COEF_R41B 0x41B +#define AU8522_FILTER_COEF_R41C 0x41C +#define AU8522_FILTER_COEF_R41D 0x41D +#define AU8522_FILTER_COEF_R41E 0x41E +#define AU8522_FILTER_COEF_R41F 0x41F +#define AU8522_FILTER_COEF_R420 0x420 +#define AU8522_FILTER_COEF_R421 0x421 +#define AU8522_FILTER_COEF_R422 0x422 +#define AU8522_FILTER_COEF_R423 0x423 +#define AU8522_FILTER_COEF_R424 0x424 +#define AU8522_FILTER_COEF_R425 0x425 +#define AU8522_FILTER_COEF_R426 0x426 +#define AU8522_FILTER_COEF_R427 0x427 +#define AU8522_FILTER_COEF_R428 0x428 +#define AU8522_FILTER_COEF_R429 0x429 +#define AU8522_FILTER_COEF_R42A 0x42A +#define AU8522_FILTER_COEF_R42B 0x42B +#define AU8522_FILTER_COEF_R42C 0x42C +#define AU8522_FILTER_COEF_R42D 0x42D /* VBI Control Registers */ -#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004 -#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005 -#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006 -#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007 +#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004 +#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005 +#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006 +#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007 #define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017 #define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018 #define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019 @@ -272,10 +272,10 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B #define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C #define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E -#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F -#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020 -#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021 -#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022 +#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F +#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020 +#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021 +#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022 #define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023 #define AU8522_REG071H 0x071 @@ -315,17 +315,17 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_GPIO_DATA_REG0E2H 0x0E2 /* Audio Control Registers */ -#define AU8522_AUDIOAGC_REG0EEH 0x0EE -#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0 -#define AU8522_AUDIO_MODE_REG0F1H 0x0F1 -#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2 -#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3 -#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4 -#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7 +#define AU8522_AUDIOAGC_REG0EEH 0x0EE +#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0 +#define AU8522_AUDIO_MODE_REG0F1H 0x0F1 +#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2 +#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3 +#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4 +#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7 #define AU8522_REG0F9H 0x0F9 -#define AU8522_AUDIOAGC2_REG605H 0x605 -#define AU8522_AUDIOFREQ_REG606H 0x606 +#define AU8522_AUDIOAGC2_REG605H 0x605 +#define AU8522_AUDIOFREQ_REG606H 0x606 /**************************************************************/ @@ -356,53 +356,53 @@ int au8522_led_ctrl(struct au8522_state *state, int led); #define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M 0x02 -#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4 #define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4 #define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4 -#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20 +#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4 +#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69 #define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68 -#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28 +#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28 /* CH1 AS Y,CH3 AS C */ -#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23 +#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23 /* CH2 AS Y,CH4 AS C */ -#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12 -#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A +#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12 +#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8 -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA -#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA +#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03 -#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03 +#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01 diff --git a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h index 855685b6b386..1ec20eecc433 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drx_driver.h +++ b/drivers/media/dvb-frontends/drx39xyj/drx_driver.h @@ -932,7 +932,7 @@ STRUCTS * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE */ struct drxu_code_info { - char *mc_file; + char *mc_file; }; /* diff --git a/drivers/media/dvb-frontends/stb0899_drv.c b/drivers/media/dvb-frontends/stb0899_drv.c index 2c5427c77db7..3c654ae16e78 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.c +++ b/drivers/media/dvb-frontends/stb0899_drv.c @@ -1583,15 +1583,15 @@ static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe) static const struct dvb_frontend_ops stb0899_ops = { .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, .info = { - .name = "STB0899 Multistandard", + .name = "STB0899 Multistandard", .frequency_min = 950000, - .frequency_max = 2150000, + .frequency_max = 2150000, .frequency_stepsize = 0, .frequency_tolerance = 0, - .symbol_rate_min = 5000000, - .symbol_rate_max = 45000000, + .symbol_rate_min = 5000000, + .symbol_rate_max = 45000000, - .caps = FE_CAN_INVERSION_AUTO | + .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | FE_CAN_2G_MODULATION | FE_CAN_QPSK diff --git a/drivers/media/dvb-frontends/stb0899_drv.h b/drivers/media/dvb-frontends/stb0899_drv.h index 6c285aee7edf..f65f9a8266f8 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.h +++ b/drivers/media/dvb-frontends/stb0899_drv.h @@ -82,7 +82,7 @@ enum stb0899_inversion { * 1. POWER ON/OFF (index 0) * 2. FE_HAS_LOCK/LOCK_LOSS (index 1) * - * @gpio = one of the above listed GPIO's + * @gpio = one of the above listed GPIO's * @level = output state: pulled up or low */ struct stb0899_postproc { diff --git a/drivers/media/dvb-frontends/stb0899_priv.h b/drivers/media/dvb-frontends/stb0899_priv.h index 86d140e4c5ed..3285cd1ba60a 100644 --- a/drivers/media/dvb-frontends/stb0899_priv.h +++ b/drivers/media/dvb-frontends/stb0899_priv.h @@ -252,7 +252,7 @@ extern int stb0899_write_s2reg(struct stb0899_state *state, extern int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable); -#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) +#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) //#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA)) /* stb0899_algo.c */ diff --git a/drivers/media/dvb-frontends/stv0900_core.c b/drivers/media/dvb-frontends/stv0900_core.c index 0b739725e3c0..72f17b97ca04 100644 --- a/drivers/media/dvb-frontends/stv0900_core.c +++ b/drivers/media/dvb-frontends/stv0900_core.c @@ -1929,7 +1929,7 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, switch (demod) { case 0: case 1: - init_params.dmd_ref_clk = config->xtal; + init_params.dmd_ref_clk = config->xtal; init_params.demod_mode = config->demod_mode; init_params.rolloff = STV0900_35; init_params.path1_ts_clock = config->path1_mode; diff --git a/drivers/media/dvb-frontends/stv0900_init.h b/drivers/media/dvb-frontends/stv0900_init.h index 411941442086..550ef4a0f654 100644 --- a/drivers/media/dvb-frontends/stv0900_init.h +++ b/drivers/media/dvb-frontends/stv0900_init.h @@ -148,8 +148,8 @@ struct stv0900_short_frames_car_loop_optim_vs_mod { /* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A, 0x1C, 0x2A, 0x3B, 0x2A, 0x1B }, { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A, @@ -176,15 +176,15 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = { 0x0B, 0x39, 0x1A, 0x19, 0x0A }, { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 }, - { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, + { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 } }; /* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x1E }, { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D, @@ -211,7 +211,7 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, - { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, + { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }, }; @@ -219,8 +219,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { /* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D, 0x0C, 0x3C, 0x0C, 0x2C, 0x0C }, { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, @@ -248,8 +248,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = { /* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */ static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = { - /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x2D, 0x1F, 0x3D, 0x3E }, { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, @@ -275,10 +275,10 @@ struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = { }; static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_QPSK_12, 0x3C, 0x2C, 0x0C, 0x2C, 0x1B, - 0x2C, 0x1B, 0x1C, 0x0B, 0x3B }, + 0x2C, 0x1B, 0x1C, 0x0B, 0x3B }, { STV0900_QPSK_35, 0x0D, 0x0D, 0x0C, 0x0D, 0x1B, 0x3C, 0x1B, 0x1C, 0x0B, 0x3B }, { STV0900_QPSK_23, 0x1D, 0x0D, 0x0C, 0x1D, 0x2B, @@ -309,8 +309,8 @@ static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = { static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ { STV0900_16APSK_23, 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A }, { STV0900_16APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, @@ -337,8 +337,8 @@ struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = { static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = { - /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon - 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/ + /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon + 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/ { STV0900_QPSK_14, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B }, { STV0900_QPSK_13, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, diff --git a/drivers/media/dvb-frontends/stv0900_priv.h b/drivers/media/dvb-frontends/stv0900_priv.h index 7a95f955627b..d1fc06ff27d3 100644 --- a/drivers/media/dvb-frontends/stv0900_priv.h +++ b/drivers/media/dvb-frontends/stv0900_priv.h @@ -243,7 +243,7 @@ struct stv0900_init_params{ u8 tun1_maddress; int tuner1_adc; - int tuner1_type; + int tuner1_type; /* IQ from the tuner1 to the demod */ enum stv0900_iq_inversion tun1_iq_inv; diff --git a/drivers/media/dvb-frontends/stv090x.c b/drivers/media/dvb-frontends/stv090x.c index 20641bd2f977..9133f65d4623 100644 --- a/drivers/media/dvb-frontends/stv090x.c +++ b/drivers/media/dvb-frontends/stv090x.c @@ -677,7 +677,7 @@ static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = { /* Cut 3.0 Short Frame Tracking CR Loop */ static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = { - /* MODCOD 2M 5M 10M 20M 30M */ + /* MODCOD 2M 5M 10M 20M 30M */ { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A }, { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 }, { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }, @@ -701,7 +701,7 @@ static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) u8 buf; struct i2c_msg msg[] = { - { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, + { .addr = config->address, .flags = 0, .buf = b0, .len = 2 }, { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 } }; @@ -4906,11 +4906,11 @@ static const struct dvb_frontend_ops stv090x_ops = { .info = { .name = "STV090x Multistandard", .frequency_min = 950000, - .frequency_max = 2150000, + .frequency_max = 2150000, .frequency_stepsize = 0, .frequency_tolerance = 0, - .symbol_rate_min = 1000000, - .symbol_rate_max = 45000000, + .symbol_rate_min = 1000000, + .symbol_rate_max = 45000000, .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | FE_CAN_QPSK | @@ -4953,7 +4953,7 @@ struct dvb_frontend *stv090x_attach(struct stv090x_config *config, state->frontend.ops = stv090x_ops; state->frontend.demodulator_priv = state; state->demod = demod; - state->demod_mode = config->demod_mode; /* Single or Dual mode */ + state->demod_mode = config->demod_mode; /* Single or Dual mode */ state->device = config->device; state->rolloff = STV090x_RO_35; /* default */ diff --git a/drivers/media/dvb-frontends/stv090x_priv.h b/drivers/media/dvb-frontends/stv090x_priv.h index 37c9f93a8a6a..fdda2185db9d 100644 --- a/drivers/media/dvb-frontends/stv090x_priv.h +++ b/drivers/media/dvb-frontends/stv090x_priv.h @@ -231,7 +231,7 @@ struct stv090x_tab { }; struct stv090x_internal { - struct i2c_adapter *i2c_adap; + struct i2c_adapter *i2c_adap; u8 i2c_addr; struct mutex demod_lock; /* Lock access to shared register */ diff --git a/drivers/media/dvb-frontends/stv6110x.c b/drivers/media/dvb-frontends/stv6110x.c index d4ac29ac9b4f..d8950028d021 100644 --- a/drivers/media/dvb-frontends/stv6110x.c +++ b/drivers/media/dvb-frontends/stv6110x.c @@ -46,7 +46,7 @@ static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) u8 b0[] = { reg }; u8 b1[] = { 0 }; struct i2c_msg msg[] = { - { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, + { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 }, { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; diff --git a/drivers/media/dvb-frontends/stv6110x_priv.h b/drivers/media/dvb-frontends/stv6110x_priv.h index a993aba27b7e..109dfaf4ba42 100644 --- a/drivers/media/dvb-frontends/stv6110x_priv.h +++ b/drivers/media/dvb-frontends/stv6110x_priv.h @@ -48,11 +48,11 @@ #define STV6110x_SETFIELD(mask, bitf, val) \ (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \ - STV6110x_OFFST_##bitf))) | \ + STV6110x_OFFST_##bitf))) | \ (val << STV6110x_OFFST_##bitf)) #define STV6110x_GETFIELD(bitf, val) \ - ((val >> STV6110x_OFFST_##bitf) & \ + ((val >> STV6110x_OFFST_##bitf) & \ ((1 << STV6110x_WIDTH_##bitf) - 1)) #define MAKEWORD16(a, b) (((a) << 8) | (b)) @@ -68,7 +68,7 @@ struct stv6110x_state { struct i2c_adapter *i2c; const struct stv6110x_config *config; - u8 regs[8]; + u8 regs[8]; const struct stv6110x_devctl *devctl; }; diff --git a/drivers/media/dvb-frontends/tda10023.c b/drivers/media/dvb-frontends/tda10023.c index abe27029fe93..6c84916234e3 100644 --- a/drivers/media/dvb-frontends/tda10023.c +++ b/drivers/media/dvb-frontends/tda10023.c @@ -211,7 +211,7 @@ static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr) BDRX=1<<(24+NDEC); BDRX*=sr; - do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */ + do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */ BDR=(s32)BDRX; } |