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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:56:25 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:15 +0100
commitd2b240d3d31c66df4d2da54c75ff8e27a0e006c3 (patch)
tree49dec4359035fc854c624d1397b24d2839c7cb08 /drivers/iio/dac
parent94ec314e1bd686b669c24385ce2dbc967eb74147 (diff)
iio: dac: ad5421: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 5691b23489db ("staging:iio:dac: Add AD5421 driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-46-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
-rw-r--r--drivers/iio/dac/ad5421.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/dac/ad5421.c b/drivers/iio/dac/ad5421.c
index eedf661d32b2..7644acfd879e 100644
--- a/drivers/iio/dac/ad5421.c
+++ b/drivers/iio/dac/ad5421.c
@@ -72,13 +72,13 @@ struct ad5421_state {
struct mutex lock;
/*
- * DMA (thus cache coherency maintenance) requires the
+ * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
- } data[2] ____cacheline_aligned;
+ } data[2] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_event_spec ad5421_current_event[] = {