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authorJames Zhu <James.Zhu@amd.com>2018-10-09 13:05:15 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-10-12 12:55:01 -0500
commitf5c5451fefceb24f2969d9f3ad6ef4c591d0272e (patch)
treeef9829d9ff24a58fdc3aaec76ea0674a79f74ca9 /drivers/gpu
parentfe146873f545f28b6c53e1d2405fc6816d5301ea (diff)
drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start
Apply new UMC enable for VNC Dynamic Power Gate mode start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5740cca49f21..624a255cffa3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1023,13 +1023,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
- /* enable UMC */
- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
- 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
-
/* boot up the VCPU */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
+ /* enable UMC */
+ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
+ 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
+ 0xFFFFFFFF, 0);
+
/* enable master interrupt */
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);