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authorGuilherme G. Piccoli <gpiccoli@igalia.com>2023-03-30 11:40:45 -0300
committerAlex Deucher <alexander.deucher@amd.com>2023-04-11 18:03:44 -0400
commit89317d4255122f05aaa0ac16d189a9ab3022653c (patch)
tree39004285f8baf157fd93c3a3186d61bd16e84737 /drivers/gpu/drm
parent207bbfb63dc0eb491f71e96baa5db9c25626a247 (diff)
drm/amd/pm: Fix incorrect comment about Vangogh power cap support
The comment mentions that power1 cap attributes are not supported on Vangogh, but the opposite is indeed valid: for APUs, only Vangogh is supported. While at it, also fixed the Renoir comment below (thanks Melissa for noticing that!). Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: Melissa Wen <mwen@igalia.com> Signed-off-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/pm/amdgpu_pm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e011041e3ec6..58c2246918fd 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -3395,7 +3395,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
effective_mode &= ~S_IWUSR;
- /* not implemented yet for GC 10.3.1 APUs */
+ /* In the case of APUs, this is only implemented on Vangogh */
if (((adev->family == AMDGPU_FAMILY_SI) ||
((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) &&
(attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
@@ -3404,7 +3404,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
return 0;
- /* not implemented yet for APUs having <= GC 9.3.0 */
+ /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
if (((adev->family == AMDGPU_FAMILY_SI) ||
((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
(attr == &sensor_dev_attr_power1_average.dev_attr.attr))