diff options
| author | Matthew Auld <matthew.auld@intel.com> | 2024-07-03 13:43:38 +0100 |
|---|---|---|
| committer | Matthew Auld <matthew.auld@intel.com> | 2024-07-05 09:53:12 +0100 |
| commit | 01570b446939c3538b1aa3d059837f49fa14a3ae (patch) | |
| tree | b054e1761166c40370ba8a456549648cdc4f351e /drivers/gpu/drm/xe/xe_device.h | |
| parent | 3078d9c8b6a0939bc732fd1c36ef86c0178127dd (diff) | |
drm/xe/bmg: implement Wa_16023588340
This involves enabling l2 caching of host side memory access to VRAM
through the CPU BAR. The main fallout here is with display since VRAM
writes from CPU can now be cached in GPU l2, and display is never
coherent with caches, so needs various manual flushing. In the case of
fbc we disable it due to complications in getting this to work
correctly (in a later patch).
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240703124338.208220-3-matthew.auld@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_device.h')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_device.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index bb07f5669dbb..0a2a3e7fd402 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -162,6 +162,7 @@ u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address); u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address); void xe_device_td_flush(struct xe_device *xe); +void xe_device_l2_flush(struct xe_device *xe); static inline bool xe_device_wedged(struct xe_device *xe) { |