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authorDan Williams <dan.j.williams@intel.com>2022-05-27 20:51:19 -0700
committerDan Williams <dan.j.williams@intel.com>2022-07-21 17:19:24 -0700
commit391785859e7e6521f622ad8c965c9792767023bc (patch)
treeebbdac616cd6b926d65dccbb3357e5b89091e4ad /drivers/cxl/cxl.h
parent256d0e9ee4f2f14d30b93fd593cef3108b0527ca (diff)
cxl/port: Move dport tracking to an xarray
Reduce the complexity and the overhead of walking the topology to determine endpoint connectivity to root decoder interleave configurations. Note that cxl_detach_ep(), after it determines that the last @ep has departed and decides to delete the port, now needs to walk the dport array with the device_lock() held to remove entries. Previously list_splice_init() could be used atomically delete all dport entries at once and then perform entry tear down outside the lock. There is no list_splice_init() equivalent for the xarray. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165784331647.1758207.6345820282285119339.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
-rw-r--r--drivers/cxl/cxl.h12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index f1dd60c86e2a..ac950fb45dd2 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -346,7 +346,7 @@ struct cxl_port {
struct device *uport;
struct device *host_bridge;
int id;
- struct list_head dports;
+ struct xarray dports;
struct xarray endpoints;
struct cxl_dport *parent_dport;
struct ida decoder_ida;
@@ -361,20 +361,24 @@ struct cxl_port {
bool cdat_available;
};
+static inline struct cxl_dport *
+cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
+{
+ return xa_load(&port->dports, (unsigned long)dport_dev);
+}
+
/**
* struct cxl_dport - CXL downstream port
* @dport: PCI bridge or firmware device representing the downstream link
* @port_id: unique hardware identifier for dport in decoder target list
* @component_reg_phys: downstream port component registers
* @port: reference to cxl_port that contains this downstream port
- * @list: node for a cxl_port's list of cxl_dport instances
*/
struct cxl_dport {
struct device *dport;
int port_id;
resource_size_t component_reg_phys;
struct cxl_port *port;
- struct list_head list;
};
/**
@@ -417,8 +421,6 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
struct device *dport, int port_id,
resource_size_t component_reg_phys);
-struct cxl_dport *cxl_find_dport_by_dev(struct cxl_port *port,
- const struct device *dev);
struct cxl_decoder *to_cxl_decoder(struct device *dev);
struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);