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authorDan Williams <dan.j.williams@intel.com>2023-02-10 18:11:01 -0800
committerDan Williams <dan.j.williams@intel.com>2023-02-10 18:11:01 -0800
commitb8b9ffced017528bcdd262730ab10bc5084c3bb4 (patch)
tree1edb4782acb2d6704f3847181a480f375214a40f /drivers/cxl/Kconfig
parentdfd423e0a3256f88b8ea622fbbe04f91594195b6 (diff)
parent09d09e04d2fcf88c4620dd28097e0e2a8f720eac (diff)
Merge branch 'for-6.3/cxl-ram-region' into cxl/next
Include the support for enumerating and provisioning ram regions for v6.3. This also include a default policy change for ram / volatile device-dax instances to assign them to the dax_kmem driver by default.
Diffstat (limited to 'drivers/cxl/Kconfig')
-rw-r--r--drivers/cxl/Kconfig12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 9e709ecba50f..ff4e78117b31 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -104,12 +104,22 @@ config CXL_SUSPEND
depends on SUSPEND && CXL_MEM
config CXL_REGION
- bool
+ bool "CXL: Region Support"
default CXL_BUS
# For MAX_PHYSMEM_BITS
depends on SPARSEMEM
select MEMREGION
select GET_FREE_REGION
+ help
+ Enable the CXL core to enumerate and provision CXL regions. A CXL
+ region is defined by one or more CXL expanders that decode a given
+ system-physical address range. For CXL regions established by
+ platform-firmware this option enables memory error handling to
+ identify the devices participating in a given interleaved memory
+ range. Otherwise, platform-firmware managed CXL is enabled by being
+ placed in the system address map and does not need a driver.
+
+ If unsure say 'y'
config CXL_REGION_INVALIDATION_TEST
bool "CXL: Region Cache Management Bypass (TEST)"