diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2018-04-26 14:10:24 +0200 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2018-06-06 10:01:18 +0200 |
| commit | fdcb613d49321b5bf5d5a1bd0fba8e7c241dcc70 (patch) | |
| tree | 1d4a1196290518d2f3525aedba2f2aea917bfdbc /drivers/cpufreq/s3c64xx-cpufreq.c | |
| parent | 1d375b58c12f08d8570b30b865def4734517f04f (diff) | |
ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set
of private registers at offset 0x800, the current lpss_device_desc for
them already sets the LPSS_SAVE_CTX flag to have these saved/restored
over device-suspend, but the current lpss_device_desc was not setting
the prv_offset field, leading to the regular device registers getting
saved/restored instead.
This is causing the PWM controller to no longer work, resulting in a black
screen, after a suspend/resume on systems where the firmware clears the
APB clock and reset bits at offset 0x804.
This commit fixes this by properly setting prv_offset to 0x800 for
the PWM devices.
Cc: stable@vger.kernel.org
Fixes: e1c748179754 ("ACPI / LPSS: Add Intel BayTrail ACPI mode PWM")
Fixes: 1bfbd8eb8a7f ("ACPI / LPSS: Add ACPI IDs for Intel Braswell")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rafael J . Wysocki <rjw@rjwysocki.net>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/cpufreq/s3c64xx-cpufreq.c')
0 files changed, 0 insertions, 0 deletions