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| author | Stephen Boyd <sboyd@kernel.org> | 2018-06-04 12:27:44 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-04 12:27:44 -0700 |
| commit | 45ba387511149a5c71d0f720366be64898bc9129 (patch) | |
| tree | 7621758b2dfa95c07256c00b3308e9ae8b59f0fc /drivers/clk | |
| parent | 7fa50aa559dd8b79178423d8bc0a64cf4ba922bc (diff) | |
| parent | f40cc01ec9e850336ef2d6899b48b0a888483751 (diff) | |
| parent | 533dfd6050356b5c341ec058058c94301e837f45 (diff) | |
| parent | 70b7e55a19b2e05e33d7f0534f06755da9c490d9 (diff) | |
| parent | 3504395f610fa654dca7b2f37ff08a7ae2cb7a7e (diff) | |
| parent | 7705bb7176b9d12c1e8649b9b91eaaa0e95f5a34 (diff) | |
Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next
* clk-allwinner:
clk: sunxi-ng: r40: export a regmap to access the GMAC register
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: add support for H6 PRCM CCU
* clk-rockchip:
clk: rockchip: remove deprecated gate-clk code and dt-binding
clk: rockchip: use match_string() helper
* clk-tegra:
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra20: Add DEV1/DEV2 OSC dividers
* clk-berlin:
clk: berlin: switch to SPDX license identifier
* clk-qcom-mmagic:
clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
clk: qcom: Register the gdscs before the clocks
clk: qcom: gdsc: Add support for ALWAYS_ON gdscs