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authorMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-24 10:41:19 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-27 11:05:57 +0100
commit64afa89ff60844f561a8934f40f0ed93e37b6a8b (patch)
tree05a51f5e2f53250cc70e060dfd5f224d1df8cc13 /drivers/clk
parentbf3be2caa593e1e35ff8d8d5b32c2c9a6a85e1d8 (diff)
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU
In order to achieve all the rates asked by the GPU, we might need to change the parent frequency. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a33.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 0d513d2674cb..a7b3c08ed0e2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -468,7 +468,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
0x180, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
- 0x1a0, 0, 3, BIT(31), 0);
+ 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const ats_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,