summaryrefslogtreecommitdiff
path: root/drivers/clk
diff options
context:
space:
mode:
authorKathiravan Thirumoorthy <quic_kathirav@quicinc.com>2023-09-14 12:29:57 +0530
committerBjorn Andersson <andersson@kernel.org>2023-10-21 12:59:13 -0700
commite0e6373d653b7707bf042ecf1538884597c5d0da (patch)
tree5a77c64169ea3e9b05d4e3210d18e0f3ca48e578 /drivers/clk
parent5635ef0bd1052420bc659a00be6fd0c60cec5cb9 (diff)
clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/qcom/apss-ipq6018.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index 0783d1aa8efa..e6295b832686 100644
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -23,16 +23,19 @@
enum {
P_XO,
+ P_GPLL0,
P_APSS_PLL_EARLY,
};
static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
{ .fw_name = "xo" },
+ { .fw_name = "gpll0" },
{ .fw_name = "pll" },
};
static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
{ P_XO, 0 },
+ { P_GPLL0, 4 },
{ P_APSS_PLL_EARLY, 5 },
};