clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate

This removes the conversion from pdiv to hw, which is already taken
care of by _get_table_rate before this code is run. This avoids
incorrectly converting pdiv to hw twice and getting the wrong hw value.

Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
setting all the other fields.

In order to prevent regressions on earlier SoC generations, all of the
frequency tables need to be updated so that they contain the actual
divider values. If they contain hardware values these would be converted
to hardware values again, yielding the wrong value.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: fix regressions on earlier SoC generations]
Signed-off-by: Thierry Reding <treding@nvidia.com>

1 files changed, 71 insertions, 51 deletions

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 0b942e0cacc2..9411a1577d85 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -202,12 +202,12 @@ static const struct pdiv_map pllxc_p[] = {
 };
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-	{ 12000000, 624000000, 104, 0, 2, 0 },
-	{ 12000000, 600000000, 100, 0, 2, 0 },
-	{ 13000000, 600000000,  92, 0, 2, 0 }, /* actual: 598.0 MHz */
-	{ 16800000, 600000000,  71, 0, 2, 0 }, /* actual: 596.4 MHz */
-	{ 19200000, 600000000,  62, 0, 2, 0 }, /* actual: 595.2 MHz */
-	{ 26000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
+	{ 12000000, 624000000, 104, 1, 2, 0 },
+	{ 12000000, 600000000, 100, 1, 2, 0 },
+	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
+	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
+	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
+	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
 	{        0,         0,   0, 0, 0, 0 },
 };
 
@@ -254,11 +254,11 @@ static const struct pdiv_map pllc_p[] = {
 };
 
 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
-	{ 12000000, 600000000, 100, 0, 2, 0 },
-	{ 13000000, 600000000,  92, 0, 2, 0 }, /* actual: 598.0 MHz */
-	{ 16800000, 600000000,  71, 0, 2, 0 }, /* actual: 596.4 MHz */
-	{ 19200000, 600000000,  62, 0, 2, 0 }, /* actual: 595.2 MHz */
-	{ 26000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
+	{ 12000000, 600000000, 100, 1, 2, 0 },
+	{ 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
+	{ 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
+	{ 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
+	{ 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
 	{        0,         0,   0, 0, 0, 0 },
 };
 
@@ -325,11 +325,11 @@ static const struct pdiv_map pllm_p[] = {
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-	{ 12000000, 800000000, 66, 0, 1, 0 }, /* actual: 792.0 MHz */
-	{ 13000000, 800000000, 61, 0, 1, 0 }, /* actual: 793.0 MHz */
-	{ 16800000, 800000000, 47, 0, 1, 0 }, /* actual: 789.6 MHz */
-	{ 19200000, 800000000, 41, 0, 1, 0 }, /* actual: 787.2 MHz */
-	{ 26000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
+	{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
+	{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
+	{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
+	{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
+	{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
 	{        0,         0,  0, 0, 0, 0 },
 };
 
@@ -364,11 +364,11 @@ static struct div_nmp pllp_nmp = {
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-	{ 12000000, 216000000, 432, 12, 1, 8 },
-	{ 13000000, 216000000, 432, 13, 1, 8 },
-	{ 16800000, 216000000, 360, 14, 1, 8 },
-	{ 19200000, 216000000, 360, 16, 1, 8 },
-	{ 26000000, 216000000, 432, 26, 1, 8 },
+	{ 12000000, 216000000, 432, 12, 2, 8 },
+	{ 13000000, 216000000, 432, 13, 2, 8 },
+	{ 16800000, 216000000, 360, 14, 2, 8 },
+	{ 19200000, 216000000, 360, 16, 2, 8 },
+	{ 26000000, 216000000, 432, 26, 2, 8 },
 	{        0,         0,   0,  0, 0, 0 },
 };
 
@@ -392,12 +392,12 @@ static struct tegra_clk_pll_params pll_p_params = {
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-	{  9600000, 282240000, 147,  5, 0, 4 },
-	{  9600000, 368640000, 192,  5, 0, 4 },
-	{  9600000, 240000000, 200,  8, 0, 8 },
-	{ 28800000, 282240000, 245, 25, 0, 8 },
-	{ 28800000, 368640000, 320, 25, 0, 8 },
-	{ 28800000, 240000000, 200, 24, 0, 8 },
+	{  9600000, 282240000, 147,  5, 1, 4 },
+	{  9600000, 368640000, 192,  5, 1, 4 },
+	{  9600000, 240000000, 200,  8, 1, 8 },
+	{ 28800000, 282240000, 245, 25, 1, 8 },
+	{ 28800000, 368640000, 320, 25, 1, 8 },
+	{ 28800000, 240000000, 200, 24, 1, 8 },
 	{        0,         0,   0,  0, 0, 0 },
 };
 
@@ -421,20 +421,20 @@ static struct tegra_clk_pll_params pll_a_params = {
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-	{ 12000000,  216000000,  864, 12, 2, 12 },
-	{ 13000000,  216000000,  864, 13, 2, 12 },
-	{ 16800000,  216000000,  720, 14, 2, 12 },
-	{ 19200000,  216000000,  720, 16, 2, 12 },
-	{ 26000000,  216000000,  864, 26, 2, 12 },
-	{ 12000000,  594000000,  594, 12, 0, 12 },
-	{ 13000000,  594000000,  594, 13, 0, 12 },
-	{ 16800000,  594000000,  495, 14, 0, 12 },
-	{ 19200000,  594000000,  495, 16, 0, 12 },
-	{ 26000000,  594000000,  594, 26, 0, 12 },
-	{ 12000000, 1000000000, 1000, 12, 0, 12 },
-	{ 13000000, 1000000000, 1000, 13, 0, 12 },
-	{ 19200000, 1000000000,  625, 12, 0, 12 },
-	{ 26000000, 1000000000, 1000, 26, 0, 12 },
+	{ 12000000,  216000000,  864, 12, 4, 12 },
+	{ 13000000,  216000000,  864, 13, 4, 12 },
+	{ 16800000,  216000000,  720, 14, 4, 12 },
+	{ 19200000,  216000000,  720, 16, 4, 12 },
+	{ 26000000,  216000000,  864, 26, 4, 12 },
+	{ 12000000,  594000000,  594, 12, 1, 12 },
+	{ 13000000,  594000000,  594, 13, 1, 12 },
+	{ 16800000,  594000000,  495, 14, 1, 12 },
+	{ 19200000,  594000000,  495, 16, 1, 12 },
+	{ 26000000,  594000000,  594, 26, 1, 12 },
+	{ 12000000, 1000000000, 1000, 12, 1, 12 },
+	{ 13000000, 1000000000, 1000, 13, 1, 12 },
+	{ 19200000, 1000000000,  625, 12, 1, 12 },
+	{ 26000000, 1000000000, 1000, 26, 1, 12 },
 	{        0,          0,    0,  0, 0,  0 },
 };
 
@@ -490,11 +490,11 @@ static struct div_nmp pllu_nmp = {
 };
 
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-	{ 12000000, 480000000, 960, 12, 0, 12 },
-	{ 13000000, 480000000, 960, 13, 0, 12 },
-	{ 16800000, 480000000, 400,  7, 0,  5 },
-	{ 19200000, 480000000, 200,  4, 0,  3 },
-	{ 26000000, 480000000, 960, 26, 0, 12 },
+	{ 12000000, 480000000, 960, 12, 2, 12 },
+	{ 13000000, 480000000, 960, 13, 2, 12 },
+	{ 16800000, 480000000, 400,  7, 2,  5 },
+	{ 19200000, 480000000, 200,  4, 2,  3 },
+	{ 26000000, 480000000, 960, 26, 2, 12 },
 	{        0,         0,   0,  0, 0,  0 },
 };
 
@@ -519,11 +519,11 @@ static struct tegra_clk_pll_params pll_u_params = {
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 	/* 1 GHz */
-	{ 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */
-	{ 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */
-	{ 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */
-	{ 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */
-	{ 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
+	{ 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
+	{ 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
+	{ 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
+	{ 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
+	{ 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
 	{        0,          0,  0, 0, 0, 0 },
 };
 
@@ -559,6 +559,25 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 	{         0,         0,   0,  0,  0,  0 },
 };
 
+static const struct pdiv_map plle_p[] = {
+	{ .pdiv =  1, .hw_val =  0 },
+	{ .pdiv =  2, .hw_val =  1 },
+	{ .pdiv =  3, .hw_val =  2 },
+	{ .pdiv =  4, .hw_val =  3 },
+	{ .pdiv =  5, .hw_val =  4 },
+	{ .pdiv =  6, .hw_val =  5 },
+	{ .pdiv =  8, .hw_val =  6 },
+	{ .pdiv = 10, .hw_val =  7 },
+	{ .pdiv = 12, .hw_val =  8 },
+	{ .pdiv = 16, .hw_val =  9 },
+	{ .pdiv = 12, .hw_val = 10 },
+	{ .pdiv = 16, .hw_val = 11 },
+	{ .pdiv = 20, .hw_val = 12 },
+	{ .pdiv = 24, .hw_val = 13 },
+	{ .pdiv = 32, .hw_val = 14 },
+	{ .pdiv =  0, .hw_val =  0 }
+};
+
 static struct div_nmp plle_nmp = {
 	.divm_shift = 0,
 	.divm_width = 8,
@@ -581,6 +600,7 @@ static struct tegra_clk_pll_params pll_e_params = {
 	.lock_mask = PLLE_MISC_LOCK,
 	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 	.lock_delay = 300,
+	.pdiv_tohw = plle_p,
 	.div_nmp = &plle_nmp,
 	.freq_table = pll_e_freq_table,
 	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,