diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-15 14:48:41 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-15 16:39:02 -0700 |
| commit | d8c25d3a1a1d61cf433654f3632a03ddaee4f781 (patch) | |
| tree | f3073e5d22c2762ee28fa0c1fe1c1be29fefa468 /drivers/clk/qcom/clk-pll.h | |
| parent | f87dfcabc6f173cc811d185d33327f50a8c88399 (diff) | |
clk: qcom: pll: Add support for configuring SR PLLs
Some SR type PLLs need to be configured for a certain rate when
linux boots. Add support for these types of PLLs so that we can
program PLL15's rate on apq8064.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-pll.h')
| -rw-r--r-- | drivers/clk/qcom/clk-pll.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h index 0775a99ca768..3003e9962472 100644 --- a/drivers/clk/qcom/clk-pll.h +++ b/drivers/clk/qcom/clk-pll.h @@ -60,6 +60,8 @@ struct pll_config { u32 aux_output_mask; }; +void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, + const struct pll_config *config, bool fsm_mode); void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, const struct pll_config *config, bool fsm_mode); |