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author | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-04 18:54:58 +0200 |
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committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-07-09 13:49:31 +0200 |
commit | 7df533a7e3d2216e860ecf147ae8cee49bf133e9 (patch) | |
tree | 6a95385f018bca6963984ef1252fc3edc7f32ade /drivers/clk/clk-oxnas.c | |
parent | 80d396b5118f448cb2206a509aba6917691a835e (diff) |
clk: meson: add gen_clk
GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/clk-oxnas.c')
0 files changed, 0 insertions, 0 deletions