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author | Thierry Reding <thierry.reding@avionic-design.de> | 2013-03-14 16:27:05 +0100 |
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committer | Mike Turquette <mturquette@linaro.org> | 2013-04-01 11:44:38 -0700 |
commit | 0f1bc12e9eddaba2baf52d020d37670dbabe3702 (patch) | |
tree | 7236ae7d234d20f2dacefd1fb8814d06cb57cdc2 /drivers/ata/pata_ixp4xx_cf.c | |
parent | 07961ac7c0ee8b546658717034fe692fd12eefa9 (diff) |
clk: tegra: Allow PLLE training to succeed
Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/ata/pata_ixp4xx_cf.c')
0 files changed, 0 insertions, 0 deletions