diff options
| author | Chen Lu <181250012@smail.nju.edu.cn> | 2021-10-18 13:22:38 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-10-27 13:08:01 -0700 |
| commit | 64a19591a2938b170aa736443d5d3bf4c51e1388 (patch) | |
| tree | 6d15e22973f2393400af5be00117a311edad2d9d /arch | |
| parent | 3ef6ca4f354c53abf263cbeb51e7272523c294d8 (diff) | |
riscv: fix misalgned trap vector base address
The trap vector marked by label .Lsecondary_park must align on a
4-byte boundary, as the {m,s}tvec is defined to require 4-byte
alignment.
Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Fixes: e011995e826f ("RISC-V: Move relocate and few other functions out of __init")
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/kernel/head.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fce5184b22c3..52c5ff9804c5 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -193,6 +193,7 @@ setup_trap_vector: csrw CSR_SCRATCH, zero ret +.align 2 .Lsecondary_park: /* We lack SMP support or have too many harts, so park this hart */ wfi |