diff options
| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | 2016-08-01 00:58:39 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-08-04 20:22:34 +1000 |
| commit | 1a058f164348a71229afd35bb5bbbb0fb514555d (patch) | |
| tree | a6f79aa0230d495b9cb43044b1b9a0a062dce0f1 /arch | |
| parent | 2c0f99516f53911c3f2f81ab3815841e3408f11e (diff) | |
powerpc/perf: Fix incorrect event codes in power9-event-list
These have been changed in the hardware, update Linux's version.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/perf/power9-events-list.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/perf/power9-events-list.h b/arch/powerpc/perf/power9-events-list.h index cda6fcb809ca..6447dc1c3d89 100644 --- a/arch/powerpc/perf/power9-events-list.h +++ b/arch/powerpc/perf/power9-events-list.h @@ -34,15 +34,15 @@ EVENT(PM_L1_ICACHE_MISS, 0x200fd) /* Instruction Demand sectors wriittent into IL1 */ EVENT(PM_L1_DEMAND_WRITE, 0x0408c) /* Instruction prefetch written into IL1 */ -EVENT(PM_IC_PREF_WRITE, 0x0408e) +EVENT(PM_IC_PREF_WRITE, 0x0488c) /* The data cache was reloaded from local core's L3 due to a demand load */ EVENT(PM_DATA_FROM_L3, 0x4c042) /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ EVENT(PM_DATA_FROM_L3MISS, 0x300fe) /* All successful D-side store dispatches for this thread */ -EVENT(PM_L2_ST, 0x16081) +EVENT(PM_L2_ST, 0x16880) /* All successful D-side store dispatches for this thread that were L2 Miss */ -EVENT(PM_L2_ST_MISS, 0x26081) +EVENT(PM_L2_ST_MISS, 0x26880) /* Total HW L3 prefetches(Load+store) */ EVENT(PM_L3_PREF_ALL, 0x4e052) /* Data PTEG reload */ |