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authorXiang wangx <wangxiang@cdjrlc.com>2022-06-10 15:05:43 +0800
committerCatalin Marinas <catalin.marinas@arm.com>2022-06-10 16:24:15 +0100
commitbb314511b6dc0f863d6fb31ebae912ee96af7805 (patch)
treecfe5dd465992a820de204aae7e7bbda82fc41f3a /arch
parentce253b8573ce3de1278513395f07118650a49e39 (diff)
arm64/fpsimd: Fix typo in comment
Delete the redundant word 'in'. Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com> Link: https://lore.kernel.org/r/20220610070543.59338-1-wangxiang@cdjrlc.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/kernel/fpsimd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 819979398127..f1d476fa50a9 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -331,7 +331,7 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
* trapping to the kernel.
*
* When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the
- * corresponding Zn), P0-P15 and FFR are encoded in in
+ * corresponding Zn), P0-P15 and FFR are encoded in
* task->thread.sve_state, formatted appropriately for vector
* length task->thread.sve_vl or, if SVCR.SM is set,
* task->thread.sme_vl.