diff options
| author | Yi Li <yi.li@analog.com> | 2009-06-19 08:51:11 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-22 21:16:19 -0400 |
| commit | 986d6c1e05642edac81cb8cc99f36a26d16ef220 (patch) | |
| tree | 36f6b6f2af09a9c97937c198c96178c3e47620be /arch | |
| parent | bd854c077e660b5f44b5049219645042bcba61ac (diff) | |
Blackfin: drop BF535-specific text for exception 0x2A (unaligned instruction)
We don't support the BF535 at all, and the exception 0x2A text specific to
it is pretty verbose and confusing (since the behavior is simply odd), so
punt it to keep the noise down.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/include/asm/traps.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h @@ -111,9 +111,7 @@ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" #define EXC_0x2A(level) \ "Instruction fetch misaligned address violation\n" \ - level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ - level " exception, the return address provided in RETX is the destination address which is\n" \ - level " misaligned, rather than the address of the offending instruction.\n" + level " - Attempted misaligned instruction cache fetch.\n" #define EXC_0x2B(level) \ "CPLB protection violation\n" \ level " - Illegal instruction fetch access (memory protection violation).\n" |