diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2013-05-19 14:06:44 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-05-23 14:25:09 +0530 |
| commit | 006dfb3c9c44192f06093d65b3a876fa5ad1319a (patch) | |
| tree | d3ea1716d564a7390141f12b98c628cfe4b932eb /arch | |
| parent | 3e87974dec5ec25a8a4852d9292db6be659164e6 (diff) | |
ARC: Use enough bits for determining page's cache color
The current code uses 2 bits for determining page's dcache color, thus
sorting pages into 4 bins, whereas the aliasing dcache really has 2 bins
(8k page, 64k dcache - 4 way-set-assoc).
This can cause extraneous flushes - e.g. color 0 and 2.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arc/include/asm/cacheflush.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index 7d819749478c..ef62682e8d95 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -93,7 +93,7 @@ static inline int cache_is_vipt_aliasing(void) #endif } -#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3) +#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1) /* * checks if two addresses (after page aligning) index into same cache set |