diff options
| author | Chris Zankel <chris@zankel.net> | 2007-09-06 01:38:18 -0700 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2008-02-13 16:58:51 -0800 |
| commit | b67360db143448be1f6d68835c6d0cc43837667f (patch) | |
| tree | 9619e20dd17684ae5cf1d2c845b4acdc134e86be /arch/xtensa/mm/cache.c | |
| parent | 49883224f6665e2b056fc3e7325b3bba9d1ff2c4 (diff) | |
[XTENSA] Flush the page-address in update-mmu instead of user-address
The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/mm/cache.c')
| -rw-r--r-- | arch/xtensa/mm/cache.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 42bfb695a170..3ba990c67676 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -180,9 +180,9 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte) #else if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) && (vma->vm_flags & VM_EXEC) != 0) { - unsigned long vaddr = addr & PAGE_MASK; - __flush_dcache_page(vaddr); - __invalidate_icache_page(vaddr); + unsigned long paddr = (unsigned long) page_address(page); + __flush_dcache_page(paddr); + __invalidate_icache_page(paddr); set_bit(PG_arch_1, &page->flags); } #endif |