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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-01-01 19:41:55 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-06 17:48:55 -0700 |
| commit | 8f8d5745bb520c76b81abef4a2cb3023d0313bfd (patch) | |
| tree | cc287760f536fc980b7277e0a3459f9a6c6a94d3 /arch/xtensa/include/asm/cache.h | |
| parent | 8e65986dcae8c49501c1920064dc192e704248bb (diff) | |
xtensa: replace variant/core.h with asm/core.h
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/cache.h')
| -rw-r--r-- | arch/xtensa/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h index d2fd932fdb4d..b21fd133ff62 100644 --- a/arch/xtensa/include/asm/cache.h +++ b/arch/xtensa/include/asm/cache.h @@ -11,7 +11,7 @@ #ifndef _XTENSA_CACHE_H #define _XTENSA_CACHE_H -#include <variant/core.h> +#include <asm/core.h> #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH #define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE |