diff options
| author | Rich Felker <dalias@libc.org> | 2016-04-22 23:29:13 +0000 |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2016-08-05 03:29:32 +0000 |
| commit | 834da197058bebcb343320dafb8b62d416d4038c (patch) | |
| tree | 86014306af44c06b216683dfbc20aa2a8e997b18 /arch/sh | |
| parent | 5a846abad07f6f30adfa3e46c5c7a47d2e7b1e63 (diff) | |
sh: add AT_HWCAP flag for J-Core cas.l instruction
The J-Core cpu has, as an ISA extension, an atomic compare-and-swap
instruction cas.l which applications need to use (instead the imask or
gusa atomic models, which are fundamentally limited to UP) for
synchronization in order to be compatible with SMP systems. Provide a
hwcap flag so that it's possible to do runtime selection and support
both.
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/include/uapi/asm/cpu-features.h | 1 | ||||
| -rw-r--r-- | arch/sh/kernel/cpu/sh2/probe.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/cpu-features.h b/arch/sh/include/uapi/asm/cpu-features.h index 694abe490edb..2f1bc851042a 100644 --- a/arch/sh/include/uapi/asm/cpu-features.h +++ b/arch/sh/include/uapi/asm/cpu-features.h @@ -22,5 +22,6 @@ #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ +#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ #endif /* __ASM_SH_CPU_FEATURES_H */ diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index 152184007964..4205f6d42b69 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -57,6 +57,8 @@ void __ref cpu_probe(void) boot_cpu_data.dcache.entry_shift = 5; boot_cpu_data.dcache.linesz = 32; boot_cpu_data.dcache.flags = 0; + + boot_cpu_data.flags |= CPU_HAS_CAS_L; #else /* * SH-2 doesn't have separate caches |