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authorLinus Torvalds <torvalds@linux-foundation.org>2016-03-16 08:36:55 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-03-16 08:36:55 -0700
commit047486d8e7c2a7e8d75b068b69cb67b47364f5d4 (patch)
tree8c9b5f7a68128f9b9a695717e662918c1683996c /arch/s390
parent9256d5a308c95a50c6e85d682492ae1f86a70f9b (diff)
parent7cc5a5d3cd4cca0a3852d1500e8c50fe191bcc9d (diff)
Merge tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov: - Altera: L2 cache and On-Chip RAM support (Thor Thayer). - EDAC: Workqueue handling cleanups (Borislav Petkov). - Xgene: Register bus error handling (Loc Ho). - Misc small fixes. * tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: ARM: socfpga: Enable OCRAM ECC on startup ARM: socfpga: Enable L2 cache ECC on startup ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries EDAC, altera: Add Altera L2 cache and OCRAM support EDAC: Use edac_debugfs_remove_recursive() in edac_debugfs_exit() EDAC, mpc85xx: Silence unused variable warning EDAC: Cleanup/sync workqueue functions EDAC: Kill workqueue setup/teardown functions EDAC: Balance workqueue setup and teardown arm64: Update the APM X-Gene EDAC node with the RB register resource EDAC, xgene: Add missing SoC register bus error handling Documentation, EDAC: Update xgene binding for missing register bus EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
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