diff options
| author | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-19 10:21:01 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-07-01 07:38:18 -0700 |
| commit | e50db34efdc8cac2f17b8f5d32fddd7b58914ce6 (patch) | |
| tree | 9dda50236d992a17e0c337e9249998a871420c66 /arch/riscv | |
| parent | bcc8790057c1f02d20654f68d107973405c1f823 (diff) | |
RISC-V: Fix up some vector state related build failures
I get a few build failures along the lines of
./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
19 | struct __riscv_v_ext_state v_state;
| ^~~~~~~
./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
32 | struct __riscv_extra_ext_header sc_extdesc;
The V structures in question are defined for !assembly, so let's just do
so for the others.
Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230619172101.18692-1-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/uapi/asm/sigcontext.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index 8b8a8541673a..8c8712aa9551 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -15,6 +15,8 @@ /* The size of END signal context header. */ #define END_HDR_SIZE 0x0 +#ifndef __ASSEMBLY__ + struct __sc_riscv_v_state { struct __riscv_v_ext_state v_state; } __attribute__((aligned(16))); @@ -33,4 +35,6 @@ struct sigcontext { }; }; +#endif /*!__ASSEMBLY__*/ + #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ |