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authorAlan Kao <alankao@andestech.com>2019-03-22 14:37:04 +0800
committerPalmer Dabbelt <palmer@sifive.com>2019-03-26 18:24:51 -0700
commitdbee9c9c45846f003ec2f819710c2f4835630a6a (patch)
tree8705ac53d89ebe72dcac442615db2a96ddac09f6 /arch/riscv/include/asm
parent8c2ffd9174779014c3fe1f96d9dc3641d9175f00 (diff)
riscv: fix accessing 8-byte variable from RV32
A memory save operation to 8-byte variable in RV32 is divided into two sw instructions in the put_user macro. The current fixup returns execution flow to the second sw instead of the one after it. This patch fixes this fixup code according to the load access part. Signed-off-by: Alan Kao<alankao@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Cc: Vincent Chen <deanbo422@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm')
-rw-r--r--arch/riscv/include/asm/uaccess.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
index a00168b980d2..fb53a8089e76 100644
--- a/arch/riscv/include/asm/uaccess.h
+++ b/arch/riscv/include/asm/uaccess.h
@@ -300,7 +300,7 @@ do { \
" .balign 4\n" \
"4:\n" \
" li %0, %6\n" \
- " jump 2b, %1\n" \
+ " jump 3b, %1\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .balign " RISCV_SZPTR "\n" \