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authorConor Dooley <conor.dooley@microchip.com>2022-06-17 19:24:25 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2022-07-14 11:06:59 -0700
commit9009f55bc44e4cb6f94e8e3315e85ad5ed69a519 (patch)
tree22895e89b0f7c25d3d9479390ce9009c96a30ffe /arch/riscv/configs/defconfig
parent54f0f3b298e21ca9a5684aa120e6bcf70e66f0c5 (diff)
riscv: config: enable SOC_STARFIVE in defconfig
SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options as it is not enabled in the default defconfig. Add it to make catching dt regressions etc easier. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220617182424.324276-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/configs/defconfig')
-rw-r--r--arch/riscv/configs/defconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 0cc17db8aaba..f8d7d9527c6e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -18,6 +18,7 @@ CONFIG_EXPERT=y
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y