diff options
| author | Vincent Chen <vincent.chen@sifive.com> | 2021-03-22 22:26:04 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-04-26 08:24:56 -0700 |
| commit | 1a0e5dbd3723e1194cc549def69fe7b557d4c72b (patch) | |
| tree | 6dc387216e93b22faaeb1ced56ce0b00b40aad8d /arch/riscv/Kconfig.erratas | |
| parent | 6f4eea90465ad0cd5f3d041b9b2c728426f2b8d4 (diff) | |
riscv: sifive: Add SiFive alternative ports
Add required ports of the Alternative scheme for SiFive.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/Kconfig.erratas')
| -rw-r--r-- | arch/riscv/Kconfig.erratas | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 4d0bafc536df..302e7467f302 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -9,4 +9,14 @@ config RISCV_ERRATA_ALTERNATIVE code patching is performed once in the boot stages. It means that the overhead from this mechanism is just taken once. +config ERRATA_SIFIVE + bool "SiFive errata" + depends on RISCV_ERRATA_ALTERNATIVE + help + All SiFive errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all SiFive errata. Please say "Y" + here if your platform uses SiFive CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + endmenu |