diff options
| author | John Crispin <blogic@openwrt.org> | 2016-01-04 20:24:00 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-01-20 00:39:20 +0100 |
| commit | 3b2e7c7c83873f4c073d501c2fff80518e264240 (patch) | |
| tree | c30c85e989e2c174aa4f1e46ee7975ce929bab71 /arch/mips/ralink/rt305x.c | |
| parent | 3bca798b859c75063b3b4e65f6b019c7a4bd53ef (diff) | |
MIPS: ralink: Add a few missing clocks
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11995/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink/rt305x.c')
| -rw-r--r-- | arch/mips/ralink/rt305x.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index 9e4572592065..d7c4ba43a428 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -201,6 +201,7 @@ void __init ralink_clk_init(void) ralink_clk_add("cpu", cpu_rate); ralink_clk_add("sys", sys_rate); ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000b40.spi", sys_rate); ralink_clk_add("10000100.timer", wdt_rate); ralink_clk_add("10000120.watchdog", wdt_rate); ralink_clk_add("10000500.uart", uart_rate); |