diff options
| author | Peter Zijlstra <peterz@infradead.org> | 2020-01-31 13:45:37 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert@linux-m68k.org> | 2020-02-10 10:57:48 +0100 |
| commit | ef9285f69f0efbc75d01cbb09fe65882effd0a25 (patch) | |
| tree | 79be6657cea036325005b2be529dac70299383e8 /arch/m68k/include | |
| parent | ef22d8abd876e805b604e8f655127de2beee2869 (diff) | |
m68k: mm: Improve kernel_page_table()
With the PTE-tables now only being 256 bytes, allocating a full page
for them is a giant waste. Start by improving the boot time allocator
such that init_mm initialization will at least have optimal memory
density.
Much thanks to Will Deacon in help with debugging and ferreting out
lost information on these dusty MMUs.
Notes:
- _TABLE_MASK is reduced to account for the shorter (256 byte)
alignment of pte-tables, per the manual, table entries should only
ever have state in the low 4 bits (Used,WrProt,Desc1,Desc0) so it is
still longer than strictly required. (Thanks Will!!!)
- Also use kernel_page_table() for the 020/030 zero_pgtable case and
consequently remove the zero_pgtable init hack (will fix up later).
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.768263973@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/motorola_pgtable.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h index 4d94e462bb2b..2ad0f4166841 100644 --- a/arch/m68k/include/asm/motorola_pgtable.h +++ b/arch/m68k/include/asm/motorola_pgtable.h @@ -23,7 +23,18 @@ #define _DESCTYPE_MASK 0x003 #define _CACHEMASK040 (~0x060) -#define _TABLE_MASK (0xfffffe00) + +/* + * Currently set to the minimum alignment of table pointers (256 bytes). + * The hardware only uses the low 4 bits for state: + * + * 3 - Used + * 2 - Write Protected + * 0,1 - Descriptor Type + * + * and has the rest of the bits reserved. + */ +#define _TABLE_MASK (0xffffff00) #define _PAGE_TABLE (_PAGE_SHORT) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE) |