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authorGuo Ren <guoren@linux.alibaba.com>2020-09-07 06:20:18 +0000
committerGuo Ren <guoren@linux.alibaba.com>2021-01-12 09:52:40 +0800
commit0c8a32eed1625a65798286fb73fea8710a908545 (patch)
tree69992b6e217f5e985ebbf1f739b2af336d89138c /arch/csky/mm/fault.c
parent7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff)
csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky: - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk) - Use SSEG0/1 (Simple Segment Mapping) We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1 are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0 to use 2G-2.5G as TLB user mapping. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/mm/fault.c')
-rw-r--r--arch/csky/mm/fault.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/csky/mm/fault.c b/arch/csky/mm/fault.c
index 081b178b41b1..94eac13b9c97 100644
--- a/arch/csky/mm/fault.c
+++ b/arch/csky/mm/fault.c
@@ -59,7 +59,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
si_code = SEGV_MAPERR;
-#ifndef CONFIG_CPU_HAS_TLBI
/*
* We fault-in kernel-space virtual memory on-demand. The
* 'reference' page table is init_mm.pgd.
@@ -84,10 +83,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
pmd_t *pmd, *pmd_k;
pte_t *pte_k;
- unsigned long pgd_base;
-
- pgd_base = (unsigned long)__va(get_pgd());
- pgd = (pgd_t *)pgd_base + offset;
+ pgd = get_pgd() + offset;
pgd_k = init_mm.pgd + offset;
if (!pgd_present(*pgd_k))
@@ -110,7 +106,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
goto no_context;
return;
}
-#endif
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
/*