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authorGraf Yang <graf.yang@analog.com>2010-03-19 08:01:27 +0000
committerMike Frysinger <vapier@gentoo.org>2011-03-22 21:03:16 -0400
commit1e924e2f1e073684b845c95886183bac6a992fb0 (patch)
treee764b69eda5a2e1d36671257995a566f027313df /arch/blackfin
parentf741a79e982cf56d7584435bad663553ffe6715f (diff)
Blackfin: SMP: flush CoreB cache when shutting down
When CoreB wakes up, it needs to read variables that CoreA might have modified, and might be in CoreB's cache. So kill CoreB's cache before going to sleep so that when we wake up, we are in a coherent state. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf561/hotplug.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index 42fc085629c7..0123117b8ff2 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -7,6 +7,7 @@
#include <linux/smp.h>
#include <asm/blackfin.h>
+#include <asm/cacheflush.h>
#include <mach/pll.h>
int hotplug_coreb;
@@ -14,8 +15,16 @@ int hotplug_coreb;
void platform_cpu_die(void)
{
unsigned long iwr;
+
hotplug_coreb = 1;
+ /*
+ * When CoreB wakes up, the code in _coreb_trampoline_start cannot
+ * turn off the data cache. This causes the CoreB failed to boot.
+ * As a workaround, we invalidate all the data cache before sleep.
+ */
+ blackfin_invalidate_entire_dcache();
+
/* disable core timer */
bfin_write_TCNTL(0);