diff options
| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-09-13 13:22:47 +0900 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-09-28 22:41:35 +0200 |
| commit | 97837505f067e9abcb2cc8b9c0a31e5330a36a36 (patch) | |
| tree | 6cf02c8794626a1ec19bdeabe0a6bf86aee96762 /arch/arm | |
| parent | d5566de59bddde675e91fa912aaa928d7e9ee277 (diff) | |
ARM: dts: uniphier: Add ahci controller nodes for PXs2
Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.
This supports for PXs2 and the boards without PXs2 vodka board that
doesn't implement any SATA connectors.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042249.4708-8-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/uniphier-pxs2.dtsi | 40 |
2 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index 759384b60663..5f18b926c50a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -99,3 +99,7 @@ &usb1 { status = "okay"; }; + +&ahci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index d2a2468d4ea0..ca4dccf56a67 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -599,6 +599,46 @@ }; }; + ahci: sata@65600000 { + compatible = "socionext,uniphier-pxs2-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 28>; + resets = <&sys_rst 28>, <&ahci_rst 0>; + ports-implemented = <1>; + phys = <&ahci_phy>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci_phy: sata-phy@10 { + compatible = "socionext,uniphier-pxs2-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; |