diff options
| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-12-11 17:25:35 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-12-13 07:51:29 -0600 |
| commit | 729cfcf8ac2447f175eb4b6a0604983618ba07d5 (patch) | |
| tree | 58084d1fca7e6eed8bbfa96e63b725cac68cabd7 /arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | |
| parent | 3942697901eb5340dc51202352f035ae191c37f2 (diff) | |
arm64: dts: ti: k3-j721s2-evm: Add overlay for PCIE1 Endpoint Mode
Add overlay to enable the PCIE1 instance of PCIe on J721S2-EVM in
Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231211115535.1264353-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso new file mode 100644 index 000000000000..43568eb67d93 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status = "disabled"; +}; + +&cbass_main { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; +}; |