diff options
| author | Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> | 2020-06-09 19:00:29 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-07-27 13:54:39 -0700 |
| commit | 015156e689aa1f0c836f9ef4d342b6f6897afd74 (patch) | |
| tree | 2d303ad9977011bf4a6e9f82e236848d059a3dbd /arch/arm64/boot/dts/qcom/sc7180.dtsi | |
| parent | 072ce1722684f3da8e16bc1ee6471a2a8affb9bd (diff) | |
arm64: dts: qcom: sc7180: Add iommus property to ETR
Define iommus property for Coresight ETR component in
SC7180 SoC with the SID and mask to enable SMMU
translation for this master.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/2312c9a10e7251d69e31e4f51c0f1d70e6f2f2f5.1591708204.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7180.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7097907a8379..9ad6752c57f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2127,6 +2127,7 @@ etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x04a0 0x20>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; |