Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC DT updates from Arnd Bergmann:
 "There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
  the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
  already supported chips.

  The other six new SoCs are all part of existing arm64 families, but
  are somewhat more interesting:

   - Samsung ExynosAutov920 is an automotive chip, and the first one we
     support based on the Cortex-A78AE core with lockstep mode.

   - Google gs101 (Tensor G1) is the chip used in a number of Pixel
     phones, and is grouped with Samsung Exynos here since it is based
     on the same SoC design, sharing most of its IP blocks with that
     series.

   - MediaTek MT8188 is a new chip used for mid-range tablets and
     Chromebooks, using two Cortex-A78 cores where the older MT8195 had
     four of them.

   - Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
     phone SoC and the first supported chip based on Cortex-X4,
     Cortex-A720 and Cortex-A520.

   - Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop
     chip using the custom Oryon cores.

   - Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
     Cortex-A76 and Cortex-A55

  In terms of boards, we have

   - Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
     G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.

   - Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy
     RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub
     and a few Rockchips SBCs

   - Some ComXpress boards based on Marvell CN913x, which is the
     follow-up to Armada 7xxx/8xxx.

   - Six new industrial/embedded boards based on NXP i.MX8 and i.MX9

   - Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.

   - Toradex Verdin AM62 Mallow carrier for TI AM62

   - Huashan Pi board based on the SophGo CV1812H RISC-V chip

   - Two boards based on Allwinner H616/H618

   - A number of reference boards for various added SoCs from Qualcomm,
     Mediatek, Google, Samsung, NXP and Spreadtrum

  As usual, there are cleanups and warning fixes across all platforms as
  well as added features for several of them"

* tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits)
  ARM: dts: usr8200: Fix phy registers
  arm64: dts: intel: minor whitespace cleanup around '='
  arm64: dts: socfpga: agilex: drop redundant status
  arm64: dts: socfpga: agilex: add unit address to soc node
  arm64: dts: socfpga: agilex: move firmware out of soc node
  arm64: dts: socfpga: agilex: move FPGA region out of soc node
  arm64: dts: socfpga: agilex: align pin-controller name with bindings
  arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
  arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
  arm64: dts: socfpga: stratix10: add unit address to soc node
  arm64: dts: socfpga: stratix10: move firmware out of soc node
  arm64: dts: socfpga: stratix10: move FPGA region out of soc node
  arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
  arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
  arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
  ARM: dts: socfpga: align NAND controller name with bindings
  ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
  arm64: dts: rockchip: Fix led pinctrl of lubancat 1
  arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
  arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
  ...

1 files changed, 169 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
new file mode 100644
index 000000000000..91e104b0f865
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ9574 RDP board common device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "ipq9574.dtsi"
+
+/ {
+	aliases {
+		serial0 = &blsp1_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	regulator_fixed_3p3: s3300 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "fixed_3p3";
+	};
+
+	regulator_fixed_0p925: s0925 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <925000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "fixed_0p925";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&gpio_keys_default>;
+		pinctrl-names = "default";
+
+		button-wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&gpio_leds_default>;
+		pinctrl-names = "default";
+
+		led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tx";
+			default-state = "off";
+		};
+	};
+};
+
+&blsp1_spi0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&uart2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&rpm_requests {
+	regulators {
+		compatible = "qcom,rpm-mp5496-regulators";
+
+		ipq9574_s1: s1 {
+		/*
+		 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+		 * During regulator registration, kernel not knowing the initial voltage,
+		 * considers it as zero and brings up the regulators with minimum supported voltage.
+		 * Update the regulator-min-microvolt with SVS voltage of 725mV so that
+		 * the regulators are brought up with 725mV which is sufficient for all the
+		 * corner parts to operate at 800MHz
+		 */
+			regulator-min-microvolt = <725000>;
+			regulator-max-microvolt = <1075000>;
+		};
+
+		mp5496_l2: l2 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+	};
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&tlmm {
+	spi_0_pins: spi-0-state {
+		pins = "gpio11", "gpio12", "gpio13", "gpio14";
+		function = "blsp0_spi";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	gpio_keys_default: gpio-keys-default-state {
+		pins = "gpio37";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	gpio_leds_default: gpio-leds-default-state {
+		pins = "gpio64";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+};
+
+&usb_0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_0_qmpphy {
+	vdda-pll-supply = <&mp5496_l2>;
+	vdda-phy-supply = <&regulator_fixed_0p925>;
+
+	status = "okay";
+};
+
+&usb_0_qusbphy {
+	vdd-supply = <&regulator_fixed_0p925>;
+	vdda-pll-supply = <&mp5496_l2>;
+	vdda-phy-dpdm-supply = <&regulator_fixed_3p3>;
+
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <24000000>;
+};