diff options
| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2016-08-03 20:29:38 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-08-12 16:47:03 +0100 |
| commit | fc1473103cfa0b785dd3ff8de2430fec42cfc8ad (patch) | |
| tree | b92445c289abed453b0ac235e691e20bceaea1a9 /arch/arm/mm/cache-l2x0.c | |
| parent | 7d281b620d229486429d851b10a05da871d22e79 (diff) | |
ARM: 8592/1: cache-l2x0.c: Replace magic numbers
Replace magic numbers used for L310 Prefetch Control Register
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index cc12905ae6f8..7e624872bd6f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -710,8 +710,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id, revision < L310_CACHE_ID_RTL_R3P2) { u32 val = l2x0_saved_regs.prefetch_ctrl; /* I don't think bit23 is required here... but iMX6 does so */ - if (val & (BIT(30) | BIT(23))) { - val &= ~(BIT(30) | BIT(23)); + if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL | + L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) { + val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL | + L310_PREFETCH_CTRL_DBL_LINEFILL_INCR); l2x0_saved_regs.prefetch_ctrl = val; errata[n++] = "752271"; } |