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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-23 08:12:21 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-23 08:12:21 -0700
commitfdc76bf9b62446c9d4b00e0d355c3212b4f1b13b (patch)
treed4266abf69b2ef462b147a33d4f905055781714b /arch/arm/mach-s3c2443/clock.c
parent72441bdc76f7f71d7b75cdaa48f26dbb1f3d932e (diff)
parentf6335c43f3d7816ba2e69abce4f29c41f65bb27e (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] clps711x: add sparsemem definitions [ARM] 5315/1: Fix section mismatch warning (sa1111) [ARM] Orion: activate workaround for 88f6183 SPI clock erratum [ARM] Orion: instantiate the dsa switch driver [ARM] mv78xx0: force link speed/duplex on eth2/eth3 [ARM] remove extra brace in arch/arm/mach-pxa/trizeps4.c [ARM] balance parenthesis in header file [ARM] pxa: fix trizeps PCMCIA build [ARM] pxa: fix trizeps defconfig [ARM] dmabounce requires ZONE_DMA [ARM] 5303/1: period_cycles should be greater than 1 [ARM] 5310/1: Fix cache flush functions for ARMv4 [ARM] pxa: fix 3bca103a1e658d23737d20e1989139d9ca8973bf [ARM] pxa: fix redefinition of NR_IRQS [ARM] S3C24XX: Fix redefine of DEFINE_TIMER() in s3c24xx pwm-clock.c [ARM] S3C2443: Fix HCLK rate [ARM] S3C24XX: Serial driver debug depends on DEBUG_LL [ARM] S3C24XX: pwm-clock set_parent mask fix
Diffstat (limited to 'arch/arm/mach-s3c2443/clock.c')
-rw-r--r--arch/arm/mach-s3c2443/clock.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 2f60bf6b8d43..f854e7385e3c 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -1033,8 +1033,7 @@ void __init s3c2443_init_clocks(int xtal)
fclk = pll / s3c2443_fclk_div(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
- hclk = hclk / s3c2443_get_hdiv(clkdiv0);
- hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
+ hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);