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authorJon Hunter <jon-hunter@ti.com>2012-12-15 01:35:43 -0700
committerPaul Walmsley <paul@pwsan.com>2012-12-15 01:35:43 -0700
commit9b4fcc86941ec0c12b27fefa39dc85e32244dc64 (patch)
tree59fab13f108ab2bd3577453d020c287502966a7a /arch/arm/mach-omap2
parentba68c7eff599705b5fe3b42895dd7d2757cb368a (diff)
ARM: OMAP4: Add function table for non-M4X dplls
Currently all OMAP4 non-core DPLLs use the same function table for configuring DPLLs. For these DPLLs, the function omap4_dpll_regm4xen_recalc() is used to recalculate the DPLL rate and the function omap4_dpll_regm4xen_round_rate() is used to calculate the closest rate to that requested. However, these omap4_dpll_regm4xen_xxx() functions are only applicable to the ABE DPLL and not the other non-core DPLLs. Therefore, add a new function table for non-core DPLLs that do not include the 4X-multiplier (M4X). Please note that using these omap4_dpll_regm4x_xxx() function works for the non-M4X DPLLs today because we only check to see if the 4X multiplier is enabled when calculating the rate. However, it is planned that the dpll functions will be enhanced to enable the 4X multiplier as necessary (in order to achieve the requested rate) and so calling these functions for non-M4X dplls will no longer work. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a1f0b55b78e3..7c1ffe61ec1b 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -365,6 +365,15 @@ static struct dpll_data dpll_iva_dd = {
static struct clk dpll_iva_ck;
+static const struct clk_ops dpll_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
static struct clk_hw_omap dpll_iva_ck_hw = {
.hw = {
.clk = &dpll_iva_ck,
@@ -373,7 +382,7 @@ static struct clk_hw_omap dpll_iva_ck_hw = {
.ops = &clkhwops_omap3_dpll,
};
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_ck_ops);
static const char *dpll_iva_x2_ck_parents[] = {
"dpll_iva_ck",
@@ -426,7 +435,7 @@ static struct clk_hw_omap dpll_mpu_ck_hw = {
.ops = &clkhwops_omap3_dpll,
};
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_ck_ops);
DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
@@ -475,7 +484,7 @@ static struct clk_hw_omap dpll_per_ck_hw = {
.ops = &clkhwops_omap3_dpll,
};
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ck_ops);
DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
@@ -569,7 +578,7 @@ static struct clk_hw_omap dpll_usb_ck_hw = {
.ops = &clkhwops_omap3_dpll,
};
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops);
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_ck_ops);
static const char *dpll_usb_clkdcoldo_ck_parents[] = {
"dpll_usb_ck",