diff options
| author | Ard Biesheuvel <ardb@kernel.org> | 2022-04-20 09:55:35 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-05-20 12:32:32 +0100 |
| commit | c4f486f1e7b34b27ec578494a236061b337d50ae (patch) | |
| tree | d9b03c71b2c2b8ffd07d8e88b955b3ebc5d657c5 /arch/arm/kernel | |
| parent | 508074607c7b95b24f0adf633fdf606761bb7824 (diff) | |
ARM: 9198/1: spectre-bhb: simplify BPIALL vector macro
The BPIALL mitigation for Spectre-BHB adds a single instruction to the
handler sequence that doesn't clobber any registers. Given that these
sequences are 10 instructions long, they don't fit neatly into a
cacheline anyway, so we can simply move that single instruction to the
start of the unmitigated one, and rearrange the symbol names accordingly.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/entry-armv.S | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 6e7dfb4786e3..87cb06316aca 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -1078,6 +1078,12 @@ __kuser_helper_end: */ .macro vector_stub, name, mode, correction=0 .align 5 +#ifdef CONFIG_HARDEN_BRANCH_HISTORY +vector_bhb_bpiall_\name: + mcr p15, 0, r0, c7, c5, 6 @ BPIALL + @ isb not needed due to "movs pc, lr" in the vector stub + @ which gives a "context synchronisation". +#endif vector_\name: .if \correction @@ -1129,21 +1135,6 @@ vector_bhb_loop8_\name: isb b 2b ENDPROC(vector_bhb_loop8_\name) - -vector_bhb_bpiall_\name: - .if \correction - sub lr, lr, #\correction - .endif - - @ Save r0, lr_<exception> (parent PC) - stmia sp, {r0, lr} - - @ bhb workaround - mcr p15, 0, r0, c7, c5, 6 @ BPIALL - @ isb not needed due to "movs pc, lr" in the vector stub - @ which gives a "context synchronisation". - b 2b -ENDPROC(vector_bhb_bpiall_\name) .previous #endif |