diff options
| author | Roger Quadros <rogerq@ti.com> | 2014-08-15 16:08:36 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-11-24 07:55:27 -0800 |
| commit | 9ec49b9f2b43a09f6263c955b84419467a1d64e0 (patch) | |
| tree | 60a4d630937486ce4963437c0a79c7c3fa87e9c4 /arch/arm/boot/dts/dra7.dtsi | |
| parent | ae3c0f75089fdfe0c1cd409cacc9ecd5122a78c6 (diff) | |
ARM: dts: DRA7: Add DCAN nodes
The SoC supports 2 DCAN nodes. Add them.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 960b2c5e0df1..63bf99be1762 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -40,6 +40,8 @@ serial9 = &uart10; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + d_can0 = &dcan1; + d_can1 = &dcan2; }; timer { @@ -1400,6 +1402,25 @@ }; }; + dcan1: can@481cc000 { + compatible = "ti,dra7-d_can"; + ti,hwmods = "dcan1"; + reg = <0x4ae3c000 0x2000>; + syscon-raminit = <&dra7_ctrl_core 0x558 0>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dcan1_sys_clk_mux>; + status = "disabled"; + }; + + dcan2: can@481d0000 { + compatible = "ti,dra7-d_can"; + ti,hwmods = "dcan2"; + reg = <0x48480000 0x2000>; + syscon-raminit = <&dra7_ctrl_core 0x558 1>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clkin1>; + status = "disabled"; + }; }; }; |