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authorEugeniy Paltsev <eugeniy.paltsev@synopsys.com>2019-01-30 19:32:41 +0300
committerVineet Gupta <vgupta@synopsys.com>2019-02-25 12:10:58 -0800
commit76551468833cd5c356b1d9ff4bc9393fcf768a59 (patch)
tree8e2552cc13389bc3c90c916b0342bfac7f3a90b1 /arch/arc/include
parent4d1e7918aae59ef504f5170a4f0c7ae82339fcb2 (diff)
ARCv2: Add explcit unaligned access support (and ability to disable too)
As of today we enable unaligned access unconditionally on ARCv2. Do this under a Kconfig option to allow disable it for test, benchmarking etc. Also while at it - Select HAVE_EFFICIENT_UNALIGNED_ACCESS - Although gcc defaults to unaligned access (since GNU 2018.03), add the right toggles for enabling or disabling as appropriate - update bootlog to prints both HW feature status (exists, enabled/disabled) and SW status (used / not used). - wire up the relaxed memcpy for unaligned access Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> [vgupta: squashed patches, handle gcc -mno-unaligned-access quick]
Diffstat (limited to 'arch/arc/include')
-rw-r--r--arch/arc/include/asm/arcregs.h1
-rw-r--r--arch/arc/include/asm/irqflags-arcv2.h8
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index a27eafdc8260..0c13317af1d6 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -82,6 +82,7 @@
#define ECR_V_DTLB_MISS 0x05
#define ECR_V_PROTV 0x06
#define ECR_V_TRAP 0x09
+#define ECR_V_MISALIGN 0x0d
#endif
/* DTLB Miss and Protection Violation Cause Codes */
diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h
index 8a4f77ea3238..e66d0339e1d8 100644
--- a/arch/arc/include/asm/irqflags-arcv2.h
+++ b/arch/arc/include/asm/irqflags-arcv2.h
@@ -44,7 +44,13 @@
#define ARCV2_IRQ_DEF_PRIO 1
/* seed value for status register */
-#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
+#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
+#define __AD_ENB STATUS_AD_MASK
+#else
+#define __AD_ENB 0
+#endif
+
+#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | __AD_ENB | \
(ARCV2_IRQ_DEF_PRIO << 1))
#ifndef __ASSEMBLY__